Max10 fpga adc

hi

i guess the sample rate is fixed in max 10 onchip adc, but it is possible to make the sample rate lower

method 1:

maybe you can write hdl to control the adc, enable it =>get the result=>disable it =>wait 1us =>enable it =>get the result.....

method 2:

there are many channels for the max 10 adc, you can enable several channels to reduce the sample rate, for example,

if the sample rate you want is 0.5MSPs, the analoge signal is in channel 0

then you can enable both channel 0 and channel 1 , then make the sequencer

slot 1 => CH0

slot 2 => CH1

the alter has a reference design for how to use the max10 adc in quartus by verilog (not in nios system)

https://cloud.altera.com/devstore/platform/?acds_version=14.1.0

ADC and Audio Monitor

hope my advise helpful!

if it really helps, please let me know!