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Ok, this sounds like the solution to my problem. There is some mention of how to shut down the core of the device and enter a sleep mode in this design note
https://www.altera.com/en_us/pdfs/li...ug_m10_pwr.pdf. However, this power management function does not appear to be a MegaFunction that I can select from Quartus. It looks like custom source code from Altera. So, I will have to download it and see if I can compile it.
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It doesn't look like the MAX10 power management function will reduce the static power consumption of a design with standard CMOS I/Os, except for outputs sourcing current to external loads. The relevant functions are gating of core clocks and shutting IOs with static current consumption like LVDS and SSTL.
A previous discussion point has been that tri-stated inputs floating to mid-level can cause additional input buffer power dissipation. You could try if the power consumption of your design decreases if you drive the 'Z' outputs to '0' or '1', or apply clear high or low level externally.
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