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Altera_Forum
Honored Contributor
9 years agoYes, I did read the data sheet. But, there is no mention of static power usage. Not that I could find.
I declare six I/O's as outputs in the source code. Then assign them to "z". Verilog code: module EPT_4CE6_AF_D1_Top ( output wire [2:0] XIO_1, output wire [2:0] XIO_2, ); assign XIO_1 = 3'hz; assign XIO_2 = 3'hz; ); endmodule The rest of the I/O's are unused in pin setting in the Device settings.