Max10 10M04 on-chip-flash erase failure

Hi,

I have modified the state machine as you have suggested to add the following states:

ERASE_UNLOCK_WAIT - Do nothing "csr_wen" and "csr_ren" both low
ERASE_UNLOCK_READ - Read the status register "cfm_csr_wen" low, "csr_ren" and "csr_addr" high
ERASE_UNLOCK_CHECK - Status register read value is valid on "csr_rdata"

I have attached the updated fpga_updater.vhd file along with some jpegs of the simulation results. Although this hasn't resolved the problem, it is interesting that the read of the status register returned the correct write protect bits cleared but with bits 31 to 28 set to 0, see file "Erase Status Reg Read 10M04.JPG". From the "Intel MAX 10 User Flash Memory User Guide" page 24 I would have expected these bits to be returned as '1'.

You can see in the file "Erase Fail 10M04.JPG" that the flash busy signal (bits 0-1 of the csr_rdata bus) transitions to BUSY_ERASE with bit 0 set on the third clock cycle in state ERASE_WAIT_3, after the state ERASE_START has programmed the control register with the sector erase. You can see the erase fail after five clock cycles when the flash_busy signal transitions back to IDLE (0).

For comparison I ran the simulation with the 10M02 model. You can see in the file "Erase Status Reg Read 10M02.JPG" that the behavior of the control register read back is the same as in the 10M04, with bits 31 to 28 set to 0. however the read then goes on to be successful, taking arround 2.5ms as can be seen in the file "Erase Full 10M02.JPG".

File "Erase Successful 10M02.JPG" shows the end of the successful erase cycle with erase successful transitions high at the first marker followed by the flash_busy signal changing from BUSY_ERASE (1) to IDLE (0) five clock cycles later at the second marker.

Thank you for your continued support,