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RichJ's avatar
RichJ
Icon for New Contributor rankNew Contributor
5 years ago

Max10 10M04 on-chip-flash erase failure

Hi, I have written a FPGA updater to write to CFM0 using a state machine and the On-Chip Flash Intel FPGA IP. This works well for the the 10M02SC part. However we have moved to the 10M04SA part and...
JohnT_Altera's avatar
JohnT_Altera
Icon for Regular Contributor rankRegular Contributor
5 years ago

Hi,


The 10M02 and 10M04 is having different architecture. May I know if the simulation loaded is the same?


Have you tested it on hardware?


  • RichJ's avatar
    RichJ
    Icon for New Contributor rankNew Contributor
    5 years ago

    Hi,

    I have generated the IP component along with its simulation model for both the 10M02 and the 10M04SA using platform designer. The test bench requires a slight modification to instance the correct flash model, and to reduce the address bus width connected to the flash component for the 10M02SC. The correct flash unlock and flash erase control register values, along with the appropriate CFM0 address ranges need to be uncommented in the device_pkg.vhdl file.

    I have attached zip files of the IP I have generated in platform designer (int_flash_ctl_10M02.zip & int_flash_ctl_10M04.zip). I believe the configuration is defined by the generic map values of the onchip_flash_0 instance in the file int_flash_ctl_10M04\int_flash_ctl_10M04\simulation\int_flash_ctl_10M04.vhd, and the equivalent file in the 10M02 IP.

    I have also checked the protection bits read back from the status register. They are correct to allow read and write access to the CFM0 sector. Sector 3 for the 10M02 part and Sector 4 for the 10M04 part.

    I have tested the appropriate code on both the 10M02 and 10M04 hardware with the same result. On the 10M02 device I can erase and reprogram the CFM0 flash, but on the 10M04 it fails to erase the CFM0 flash.