Hi All, I am new to the Altera CPLDs. Come from the X-Company side of things. The Max V CPLD looks really cool. What with user Flash memory, Internal programmable Oscillator, low power states. Is there a DPLL available on these devices. I found references to that on the product landing page but the data sheet does not talk about that. Can someone please clarify? thanks ANanth

MAX V effectively is MAX II, with identical specification and core structure, and minimal changes, extending Z (zero power) to higher densities and introducing new packages. Rated number of programming cycles has been gracefully increased from 100 to 1000 for the UFM. MAX II/V has an internal RC oscillator, required for operation of the internal flash and also exposed to user logic. It's not programmable. No new clock processing features are provided according to the datasheet. The DPLL point is interesting indeed. It still written on the MAX V product page. http://www.altera.com/products/devices/cpld/max-v/mxv-index.jsp --- Quote Start --- ...features including: Digital PLLs (DPLLs), which enable flexible implementation of designs requiring frequency multiplication or phase shifting --- Quote End --- It's also written in the MAX V solution sheet http://www.altera.com/literature/po/ss-maxv-cplds.pdf --- Quote Start --- MAX V Silicon Features and Benefits ... Phase-locked loops (PLLs) - Digital PLL implementation provides flexible implementation for designs needing frequency multiplication or phase shifting. --- Quote End --- So either the "clock network" chapter has been forgotten in the MAX V datasheet, or the feature has been previously planned but wasn't implemented, or it has been implemented, but doesn't work.

The DPLL feature on MAX V devices is interesting. However, the overview page has this note: --- Quote Start --- Note: 1. Digital PLL is an optional intellectual property (IP) that can be instantiated into unused LEs. --- Quote End --- So is it just an IP feature? No specific silicon support? If that is the case, then why it is specific and restricted to MAX V?

Hi All, Thanks for chiming in. How does the "instantiating optional IP" generally work with the A devices? Is it one within Quartus, like Megacore function maybe?? With X devices it is done by Coregen. But Coregen is restricted to FPGAs only not for the Coolrunner-II CPLDs. thanks Ananth

--- Quote Start --- the overview page has this note --- Quote End --- Where did you read this? Generally, MAX II as well as MAX V are small SRAM based FPGAs rather classical CPLDs, the device core is almost identical to Cyclone III, but it lacks internal RAM, hardware PLLs and some interface types. In so far, the prerequisites to create a PLL in LEs would be the same for Cyclone or MAX II/V devices. In the above quoted document a functionality similar to the dedicated hardware PLLs of Cyclone and Stratix FPGA is described (e.g. allowing frequency multiplication and phase shifting). It can't be done will discrete time PLLs, that are suitable for low output frequencies at a fraction of the input clock only. There's a principle method to implement a PLL in ASIC gates respectively FPGA logic cells by utilizing programmable delay line oscillators. German company Chip Cologne has filed a patent for it and is selling it as an ASIC IP. http://www.colognechip.com/asic/ip-cores/digicc-pll-techn.pdf But it seems unlikely, that this technique has been intended for the said MAX V PLLs. As expectable, Altera Quartus V10.1 does not provide a DPLL Megafunction for MAX V.

--- Quote Start --- Where did you read this? --- Quote End --- As I said, it is in the Max V overview page: http://www.altera.com/products/devices/cpld/max-v/overview/mxv-overview.html --- Quote Start --- In the above quoted document a functionality similar to the dedicated hardware PLLs of Cyclone and Stratix FPGA is described (e.g. allowing frequency multiplication and phase shifting). It can't be done will discrete time PLLs, that are suitable for low output frequencies at a fraction of the input clock only. --- Quote End --- I agree. But the fact is that Altera is claiming it is an IP, and Altera documentation doesn't mention, so far, any silicon support. So something seems wrong, but we don't really know exactly what.

Max v cpld dpll | Altera Community

13 Replies

Altera_Forum
Honored Contributor
15 years ago
Typically, I don't line up as a first implementer. But if I had the device under my fingertips, I most likely won't be aware of hidden or unsupported features. Apart from the zero power feature, everything in the device handbook looks similar to MAX II.

Actually having the DPLL option would open new applications for the device, so I'm seriously interested now. A recent update to my support request (from sunday) promises an early reply. I'll keep you informed. If anyone else got substantial news from Altera in the meantime, I would be glad to hear about.

Regards,
Frank
Altera_Forum
Honored Contributor
15 years ago
Support says:

--- Quote Start ---
Regarding your MAX V Digital PLL request, unfortunately our marketing and engineering teams still is in progress characterizing and finalizing the details. We do not have much information to share out at this moment. The tentative target for this feature to be supported by Quartus II software will be by end of this year.
--- Quote End ---

Apparently, the MAX V product pages are missing a preview title line.

Forum Discussion

Max v cpld dpll

13 Replies

Recent Discussions

HSIO Differential Clock Output VOD and VOCM

Suche Programmierspezifikation für Altera EPM5130QC-1 / CY7C346 (MAX5000)

Inquiry Regarding MAX 10 TDO Output Level During JTAG Operation

Quartus Programmer 21.1: JTAG Server Error Code 82 – Port 1309 Cannot Be Bound

Unable to Generate Valid PAM4 Eye Diagram and BER Measurements on Stratix 10 SI E-Tile Native PHY