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Altera_Forum
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9 years ago

MAX FPGA/CPLD capable of dynamic signal shifting, 3.3v -> 1.8v on same GPIO?

Wondering if the MAX series 10 FPGA or 5 CPLD are capable of dynamic signal shifting on the same GPIO. Ex. signaling at 3.3v for initialization and then switching to 1.8v for data transfer?
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
9 years ago

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would it be better to have two I/O banks connected in parallel with a diode to the interface?

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No diodes, just parallel a 1.8 and 3.3V driver. Take care that one driver is three-stated when the other is driving out.

Finally, if you don't need high speed, you can either use a single 1.8V driver with pull-up to 3.3V or vice versa. Three-stating the output activates the pull-up level.