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Altera_Forum
Honored Contributor
11 years agoAll four are dedicate input pins. So, don't leave them floating.
From the datasheet: --- Quote Start --- each register clear function can be individually driven by the active-low dedicated global clear pin (GCLRn). --- Quote End --- This implies it is not something you can control inside your design. So, tie this high. My, relatively rusty, first hand experience of this family reminds me that that is the case. GCLK, OE1 & OE2 can be tied to GND. Put your design together and run it through Quartus. The report files will confirm what you're expected to do with all the pins, whether they're used by your design or not. Cheers, Alex