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ARitt
New Contributor
New ContributorMAX 10 Sample & Hold Timing
The MAX 10 A/D block diagram shows a sample and hold function before the A/D. Unfortunately, there is no documentation of the timing for the S/H function. When sampling a complex signal, it is impo...
KhaiChein_Y_Intel
Regular Contributor
Regular ContributorHi ARitt,
The input clock frequencies are 2 MHz, 10 MHz, 20 MHz, 40 MHz, and 80 MHz.
Implementation Guide reference: https://www.intel.com/content/www/us/en/programmable/documentation/sam1393576011848.html
Thanks
