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Altera_Forum's avatar
Altera_Forum
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10 years ago

MAX 10 Pin Questions

Hello,

I am working on design using a Altera 10M50SC device and have a few questions regarding pin types.

First, this file https://www.altera.com/content/dam/altera-www/global/en_us/pdfs/literature/dp/max-10/10m50sc.pdf specifies no IO performance for pins 50,58,62 and 135. What is the IO performance of these pins?

Second, I have run into trouble with Cyclone V single-ended clock input pins where only the _p input could be used single ended. With this MAX10 device, can either the _p and _n of a clock input be used single-ended? May they *both* be used as different single-ended clocks at the same time? If one is used as a single-ended clock, may the other be used without restriction as general purpose IO?

Finally, similar to the question about clock inputs, are there any restrictions when using PLL_L_CLKOUTp and n as one or two single-ended clock outputs or single-ended clock output and the other IO?

Thanks,

Steve

2 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    10 years ago

    You'll have to ask Altera for clarification regarding the performance of the pins not covered pinout. However, you could also refer to figure 2-4 on page 2-11 of the "max 10 general purpose i/o user guide (https://www.altera.com/en_us/pdfs/literature/hb/max-10/ug_m10_gpio.pdf)". This explains the low & high speed banks break out to pins.

    As for your other questions:-

    Yes, you can use both CLKxn & CLKxp for separate single ended clock inputs.

    Yes, you can use one as a clock input and the other as general purpose I/O.

    There are restrictions around the use of the CLKOUT pins. These are associated with a particular PLL and benefit from a low latency path from the PLL out of the device. So, if you use PLL_L_CLKOUTp as a single ended output, driven directly from it's PLL, you will not be able to use is pair, PLL_L_CLKOUTn, as a single ended CLKOUT signal driven directly from a PLL. I highlight 'directly' as it may be possible to route a PLL output signal out of this pin but you will not benefit from any low latency path. However, you will be able to use it as a general purpose I/O.

    Cheers,

    Alex
  • Altera_Forum's avatar
    Altera_Forum
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    10 years ago

    Hi Alex,

    Thanks for the reply. Just to possible help others, I did run into a problem when connecting the other half of a CLKx differential pair to an output. This case is illegal:

    CLKx n or p as single ended clock connected to PLL

    CLKx p or n as output

    The error is that the output is too close to the PLL. It occurs for any CLKx pair.

    Best Regards,

    Steve