MAX 10 Pin Questions

You'll have to ask Altera for clarification regarding the performance of the pins not covered pinout. However, you could also refer to figure 2-4 on page 2-11 of the "max 10 general purpose i/o user guide (https://www.altera.com/en_us/pdfs/literature/hb/max-10/ug_m10_gpio.pdf)". This explains the low & high speed banks break out to pins.

As for your other questions:-

Yes, you can use both CLKxn & CLKxp for separate single ended clock inputs.

Yes, you can use one as a clock input and the other as general purpose I/O.

There are restrictions around the use of the CLKOUT pins. These are associated with a particular PLL and benefit from a low latency path from the PLL out of the device. So, if you use PLL_L_CLKOUTp as a single ended output, driven directly from it's PLL, you will not be able to use is pair, PLL_L_CLKOUTn, as a single ended CLKOUT signal driven directly from a PLL. I highlight 'directly' as it may be possible to route a PLL output signal out of this pin but you will not benefit from any low latency path. However, you will be able to use it as a general purpose I/O.

Cheers,

Alex