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Altera_Forum's avatar
Altera_Forum
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9 years ago

Max 10 Open Drain in analog banks

Hello, I've got a board with a 10M08SCU (no ADC) on it. I'm trying to use banks 1A and 1B to control PMOS high-side drivers. The output pin from the Max 10 is connected to the gate and pulled u...
Altera_Forum's avatar
Altera_Forum
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9 years ago

Thanks for the response. I guess I should have paid more attention to the datasheet. Based on the sections you referenced in the datasheet, I should expect a failure on my other lines in just a few days (maybe a couple weeks at best) of on time, which is the idle state for these lines.

I thought I'd be able to get away with this since I was driving them open drain, but as you mentioned, there aren't any apparent mentions of 5v in the datasheet. Unfortunately, I'm very constrained on space with this board, so I'd really like to be able to not include that external FET, and it'd be nice to be able to test on this rev with all of my hardware. Is there anything I can do to mitigate this on my current hardware, and without adding that external FET on my next rev?