Max 10 Minimum Pulse Width - Weird Behavior

@KhaiY_Intel​

I was able to answer the second question for myself. If I don't do input/output constraints, Timing Analyzer doesn't associate SCK_1, SCK_2, etc. as being "clocked" by the 62.5 MHz SPI_CLK. "They're just asynchronous signals, how would I know anything about their timing?" it says to itself, ignoring the explicit assign statement in my RTL. Thus it ignores them in the Minimum Pulse Width analysis. To confirm this, I was able to get the error to show up without input/output delays by explicitly identifying them as a clock like so:

create_clock -name {SCK_} -period 16.000 -waveform { 0.000 8.000 } [get_ports {SCK_*}]

This should be considered a bug... you would not believe the headache this caused in our design reviewing.

I'm still interested in knowing if this apparent 50 MHz maximum output frequency is documented anywhere. These pins are 3.3V LVCMOS. I don't see anything in the Max 10 datasheet. Should I be looking somewhere else?