MAX 10 LVDS and DDR

I'm trying to do more or less the same thing, interfacing the MAX 10 with an LTC2264 40 Mhz ADC.

http://cds.linear.com/docs/en/datasheet/22654312fb.pdf - page 9

The output from the ADC is LVDS serial, at double data rate, an LVDS clock signal, and an LVDS frame signal. I have several questions.

After reading the MAX 10 High-Speed LVDS manual, I'm confused as to the clocking scheme I should use for a soft LVDS receiver block. Since the ADC provides me with a serial clock, I shouldn't need to use a PLL in the LVDS block, should I? What PLL configuration should I use when configuring this IP?

Second question: word boundary alignment. The ADC has a frame output, with a differential 0 to 1 logic transition indicating the first bit of the serial word. I noticed in the MAX 10 LVDS doc that there is a data re-alignment block in the LVDS signal chain - I'm guessing that the rx_channel_data_align input should be from the ADC frame signal?

Third question: the soft LVDS module instantiation port list shows an RX serial data input with one bit per LVDS channel. Why does an LVDS block appear to take single ended inputs? I must be missing something there.

Fourth question, double rate rate. In the MAX 10 LVDS doc, there is only one mention of DDR: "For LVDS transmitters and receivers, MAX 10 devices use the the double data rate I/O (DDIO)registers that reside in the I/O elements (IOE)." Does this mean that the LVDS serial input is assumed to be using double data rate, and that I do not need to either specify DDR anywhere?

Finally, why can't I use primitives like ALTDDIO or ALT_INBUF_DIFF with the MAX 10? I have a design for this same ADC using equivalent primitives for Xilinx FPGAs, and it not only makes the HDL stupidly easy to comprehend, but would only take me about a half hour to bang out the same design for Altera if I could use them.

I would appreciate any help here.

Thanks,

Devin