Hello Aiman,
I was out for few days, hence the delayed response.
I cannot give you the whole svf file but I can do few excerpts where some of the undocumented codes are located:
!Max 10 DSM Clear
!
SIR 10 TDI (203);
RUNTEST 8 TCK;
SDR 23 TDI (000000);
SIR 10 TDI (3F2);
RUNTEST 350003 TCK;
!
!Max 10 DSM Verify
!
SIR 10 TDI (307);
RUNTEST 8 TCK;
SDR 1 TDI (0) TDO (1) MASK (1);
!
!Max 10 Program CFM1
!
SIR 10 TDI (203);
RUNTEST 8 TCK;
SDR 23 TDI (001E80);
SIR 10 TDI (2F4);
RUNTEST 8 TCK;
!
!Max 10 Program Done Bit
!
SIR 10 TDI (203);
RUNTEST 8 TCK;
SDR 23 TDI (440000);
SIR 10 TDI (3F4);
RUNTEST 8 TCK;
SDR 32 TDI (6C48A50F);
RUNTEST 320 TCK;
Again, it is not critical at this point since I was able to program the FPGA, but I found it weird not to find documentation about some of the codes used in the svf file.
Who wrote the programmer conversion function to generate svf file, must have had the information about those codes and their use.
I am not interested in any factory reserved instruction codes, but only the codes generated automatically by the Quartus Programmer.
Thank you again for your support,
Dan