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Hi,
Can you attach the Compiler report?
Elaborate more on the steps and IP's used in your design.
Refer below link for more information on Steps and IP licensing.
https://www.altera.com/content/dam/altera-www/global/en_us/pdfs/literature/an/an320.pdf Best Regards,
Anand Raj Shankar
(This message was posted on behalf of Intel Corporation)
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1. Compiler report attached.
2. This design is using Altera On-chip flash memory. After adding the IP using Qsys, I created a top level module that interfaced and instantiated the IP. And I am using standard edition of the Quartus with Open Core hardware evaluation mode enabled.