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Shweta_24's avatar
Shweta_24
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3 years ago

MAX-10 IBIS model issue

Hello team, I am working on IBIS model validation of MAX10 I have observed that the temperature ranges in IBIS file for CMOS and TTL models are same. Ideally, For CMOS temperature which causes th...
Board Debug
Mengzhe's avatar
Mengzhe
Icon for Occasional Contributor rankOccasional Contributor
3 years ago

Hi,


Thanks for your advice.

In my opinion, the difference between LVTTL and LVCMOS model is the voltage leveling difference, not meaning the difference on physical die. As you can change the output mode from LVTTL to LVCMOS in a specific GPIO pin through Quartus project, however, the structure of gate in the I/O bank has not been changed.

So, don't worry about they have different electric characteristic. The IBIS model just reflect the I-V curves under different situation.


BR,

Mengzhe


  • Shweta_24's avatar
    Shweta_24
    Icon for New Contributor rankNew Contributor
    2 years ago

    Hello Mengzhe,

    I am using MAX10 IBIS model from that model- lvttl_rio_d4s2 in this model

    the power clamp table exhibits stair-stepping .

    According to IBIS specification ,There should be no stair stepping of any I-V tables, with flat sections and abrupt jumps. This is caused by
    insufficient significant digits in the table current columns

    can you please check attached snapshot below

    Regards,

    shweta chendake