XQSHEN
Occasional Contributor
Occasional ContributorMax 10 FPGA pll output clock jitter
if I use Max 10 FPGA pll output clock as ADC driver input, what will be the clock jitter?
Hi,
The MAX 10 device datasheet specifies the jitter in the output clock in terms of following parameters:
For regular I/Os:
tOUTJITTER_PERIOD_IO - Regular I/O period jitter
tOUTJITTER_CCJ_IO - Regular I/O cycle-to-cycle jitter
For dedicated clock outputs:
tOUTJITTER_PERIOD_DEDCLK - Dedicated clock output period jitter
tOUTJITTER_CCJ_DEDCLK - Dedicated clock output cycle-to-cycle jitter
Please refer the datasheet for the numbers. https://www.intel.com/content/www/us/en/programmable/documentation/mcn1397700832153.html#mcn1397897761093
Regards
