Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
8 years ago

MAx 10, External SRAM

Hello, I connected an SRAM to MAX10. To control I wrote a very simple IP that simply remap internal Avalon-MM signals and do a tristate of data bus lines. This doesn't work event at low data r...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
7 years ago

Hi SStrel, tank a lot for assistance, that document was the first I found by googling around, at this moment I am not able to use this controller due it refuse reduce to 16 bit bus, I try more later.

About my code why

SRAM_Data <= avalon_slave_writedata when avalon_slave_write='1' else

(others => 'Z');

refuse to input/output data?

I am using similar code to read write an external bus (unrelated to SRAM) and it work fine, on RAM forever read 0 and seems not writing data to.

Next week I can collect some spare time and I test it Thorougly again to try isolate the problem from design. Using internal FPGA RAM work(final board with 10M50SC), using external DRAM (test board) it work, SRAM controller seems faulty. Again I cannot use nor NIOS nor JTAG debugger, when inserted on design refuse to compile with an error relative to Config flash, no way at this moment to inspect from internal bus, I arrange some test from external Logic Analyzer pod.

Best regards

Roberto