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Altera_Forum's avatar
Altera_Forum
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10 years ago

Max 10 clock divider

I am using the internal oscillator in the max10, and wondering whats the best way to divide it down. I looked into using a PLL for this but that doesn't seem to be possible. Is there any better app...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
9 years ago

That was my misprint dude. Actually my question was something else.I just can set the clk frequency for 55Mhz or 116Mhz but not any other frequency in the range of 55Mhz or 116Mhz. I can't use PLL for that, because the it has forbidden by the datasheet. the first question is how i can reach the frequencies in the range of the 55-116Mhz. and the second question is the practical frequency that i get from the output clk is 83.4 in the cases that i set the working frequncy of the core for 55Mhz or 116Mhz! why it's acting like this??