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Altera_Forum
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8 years ago

MAX 10: a clock for SPI

Is using an external clock without a clock buffer causing any problem? I'm implementing SPI slave. An external SPI clock is directly from a pin(not a clock pin, but just an IOpin) of the FPGA...
Altera_Forum's avatar
Altera_Forum
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7 years ago

You have no timing constraints? What 'timing violations' are being reported?

What hardware are you using? Is the FPGA your a host talking to an external slave device?

You mention a 50MHz clock. What hardware are you using?

Assuming you are trying to talk to an external slave and you'd simply like to get something working I suggest you use the 50MHz clock to clock all your logic and treat your sclk as a signal (not a clock) that you generate with logic.

You are going to need more of a state machine to implement an SPI host as well.

JRL - whilst I agree this may not be ideally coded, the code does conform to the classic clock & (asynchronous) reset in the sensitivity list with a single conditional statement (if) handling the reset (in_CSn). So, I feel Quartus will have no trouble understanding this or timing it.

Cheers,

Alex