matrix transpose code in vhdl

Dear all,

I want to transpose a set of matrix from row to column.I has write the code in VHDL but has error occured.Below is my code:

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library ieee;

use ieee.std_logic_1164.all;

entity transpose is

port (

-- Inputs

in1 : IN integer RANGE -127 TO 127;

in2 : IN integer RANGE -127 TO 127;

in3 : IN integer RANGE -127 TO 127;

in4 : IN integer RANGE -127 TO 127;

in5 : IN integer RANGE -127 TO 127;

in6 : IN integer RANGE -127 TO 127;

in7 : IN integer RANGE -127 TO 127;

in8 : IN integer RANGE -127 TO 127;

--Outputs

out1 : OUT integer RANGE -127 TO 127;

out2 : OUT integer RANGE -127 TO 127;

out3 : OUT integer RANGE -127 TO 127;

out4 : OUT integer RANGE -127 TO 127;

out5 : OUT integer RANGE -127 TO 127;

out6 : OUT integer RANGE -127 TO 127;

out7 : OUT integer RANGE -127 TO 127;

out8 : OUT integer RANGE -127 TO 127);

end transpose;

architecture transpose of transpose is

begin

for i in 1 to m loop;

for j in 1 to n loop;

Gazouta (i,j)<= Gazinta (j,i);

end loop;

end loop;

end transpose;

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Can anyone help me correct this code?Many thanks