Matrix multiply algorithm

I'm trying to implement a systolic matrix multiplication algorithm and have written the following so far. Of particular interest is the PROCESS, which has a nested IF. When I compile, it says (expected "if" where PROCESS). All of the source I've written is below.

I don't understand why I would get that error when compiling. I ENDed both IFs correctly from what I see. The components are simple, I can post them if needed.

LIBRARY ieee;

USE ieee.std_logic_1164.all;

-------------------------------------

ENTITY lab2 IS

PORT (clk, rst: IN STD_LOGIC);

END lab2;

-------------------------------------

ARCHITECTURE structure OF lab2 IS

TYPE matrix_row IS ARRAY (6 downto 0) OF std_logic_vector(3 downto 0);

TYPE matrix_west IS ARRAY (0 to 3) OF matrix_row;

TYPE matrix_north IS ARRAY (0 to 3) OF matrix_row;

TYPE matrix_done IS ARRAY (0 to 3, 0 to 3) OF std_logic_vector(7 downto 0);

CONSTANT matrix_A: matrix_west :=((X"0",X"0",X"0",X"5",X"3",X"1",X"2"),

(X"0",X"0",X"2",X"3",X"1",X"2",X"0"),

(X"0",X"1",X"2",X"3",X"4",X"0",X"0"),

(X"3",X"2",X"4",X"1",X"0",X"0",X"0"));

CONSTANT matrix_B: matrix_north :=((X"1",X"1",X"3",X"2",X"0",X"0",X"0"),

(X"0",X"3",X"2",X"1",X"2",X"0",X"0"),

(X"0",X"0",X"2",X"1",X"3",X"1",X"0"),

(X"0",X"0",X"0",X"1",X"4",X"2",X"3"));

CONSTANT matrix_result: matrix_done :=((X"00",X"00",X"00",X"00"),

(X"00",X"00",X"00",X"00"),

(X"00",X"00",X"00",X"00"),

(X"00",X"00",X"00",X"00"));

---------------------------------------------------------------------------

PORT (west, north: IN std_logic_vector(3 downto 0);

south, east: OUT std_logic_vector(3 downto 0);

result: OUT std_logic_vector(7 downto 0));

END COMPONENT;

COMPONENT adder IS

PORT (new_term: IN std_logic_vector(7 downto 0);

stored: IN std_logic_vector(7 downto 0);

result: OUT std_logic_vector(7 downto 0));

END COMPONENT;

----------------------------------------------------------------------------

SIGNAL west1, west2, west3, west4: std_logic_vector(3 downto 0);

SIGNAL north1, north2, north3, north4: std_logic_vector(3 downto 0);

SIGNAL w1_2, w2_3, w3_4, w5_6, w6_7, w7_8: std_logic_vector(3 downto 0);

SIGNAL w9_A, wA_B, wB_C, wD_E, wE_F, wF_0: std_logic_vector(3 downto 0);

SIGNAL n1_5, n2_6, n3_7, n4_8, n5_9, n6_A: std_logic_vector(3 downto 0);

SIGNAL n7_B, n8_C, n9_D, nA_E, nB_F, nC_0: std_logic_vector(3 downto 0);

SIGNAL result1, result2, result3, result4: std_logic_vector(7 downto 0);

SIGNAL result5, result6, result7, result8: std_logic_vector(7 downto 0);

SIGNAL result9, resultA, resultB, resultC: std_logic_vector(7 downto 0);

SIGNAL resultD, resultE, resultF, result0: std_logic_vector(7 downto 0);

SIGNAL store1, store2, store3, store4: std_logic_vector(7 downto 0);

SIGNAL store5, store6, store7, store8: std_logic_vector(7 downto 0);

SIGNAL store9, storeA, storeB, storeC: std_logic_vector(7 downto 0);

SIGNAL storeD, storeE, storeF, store0: std_logic_vector(7 downto 0);

SIGNAL return1, return2, return3, return4: std_logic_vector(7 downto 0);

SIGNAL return5, return6, return7, return8: std_logic_vector(7 downto 0);

SIGNAL return9, returnA, returnB, returnC: std_logic_vector(7 downto 0);

SIGNAL returnD, returnE, returnF, return0: std_logic_vector(7 downto 0);

---------------------------------------------------------------------------

BEGIN

X1: multiplier PORT MAP (west=>west1, north=>north1, south=>n1_5,

east=>w1_2, result=>result1);

X2: multiplier PORT MAP (west=>w1_2, north=>north2, south=>n2_6,

east=>w2_3, result=>result2);

X3: multiplier PORT MAP (west=>w2_3, north=>north3, south=>n3_7,

east=>w3_4, result=>result3);

X4: multiplier PORT MAP (west=>w3_4, north=>north4, south=>n4_8,

east=>OPEN, result=>result4);

X5: multiplier PORT MAP (west=>west2, north=>n1_5, south=>n5_9,

east=>w5_6, result=>result5);

X6: multiplier PORT MAP (west=>w5_6, north=>n2_6, south=>n6_A,

east=>w6_7, result=>result6);

X7: multiplier PORT MAP (west=>w6_7, north=>n3_7, south=>n7_B,

east=>w7_8, result=>result7);

X8: multiplier PORT MAP (west=>w7_8, north=>n4_8, south=>n8_C,

east=>OPEN, result=>result8);

X9: multiplier PORT MAP (west=>west3, north=>n5_9, south=>n9_D,

east=>w9_A, result=>result9);

XA: multiplier PORT MAP (west=>w9_A, north=>n6_A, south=>nA_E,

east=>wA_B, result=>resultA);

XB: multiplier PORT MAP (west=>wA_B, north=>n7_B, south=>nB_F,

east=>wB_C, result=>result;

XC: multiplier PORT MAP (west=>wB_C, north=>n8_C, south=>nC_0,

east=>OPEN, result=>resultC);

XD: multiplier PORT MAP (west=>west4, north=>n9_D, south=>OPEN,

east=>wD_E, result=>resultD);

XE: multiplier PORT MAP (west=>wD_E, north=>nA_E, south=>OPEN,

east=>wE_F, result=>resultE);

XF: multiplier PORT MAP (west=>wE_F, north=>nB_F, south=>OPEN,

east=>wF_0, result=>resultF);

X0: multiplier PORT MAP (west=>wF_0, north=>nC_0, south=>OPEN,

east=>OPEN, result=>result0);

Adder1: adder PORT MAP (new_term=>result1, stored=>return1,

result=>store1);

Adder2: adder PORT MAP (new_term=>result2, stored=>return2,

result=>store2);

Adder3: adder PORT MAP (new_term=>result3, stored=>return3,

result=>store3);

Adder4: adder PORT MAP (new_term=>result4, stored=>return4,

result=>store4);

Adder5: adder PORT MAP (new_term=>result5, stored=>return5,

result=>store5);

Adder6: adder PORT MAP (new_term=>result6, stored=>return6,

result=>store6);

Adder7: adder PORT MAP (new_term=>result7, stored=>return7,

result=>store7);

Adder8: adder PORT MAP (new_term=>result8, stored=>return8,

result=>store8);

Adder9: adder PORT MAP (new_term=>result9, stored=>return9,

result=>store9);

AdderA: adder PORT MAP (new_term=>resultA, stored=>returnA,

result=>storeA);

AdderB: adder PORT MAP (new_term=>resultB, stored=>returnB,

result=>store;

AdderC: adder PORT MAP (new_term=>resultC, stored=>returnC,

result=>storeC);

AdderD: adder PORT MAP (new_term=>resultD, stored=>returnD,

result=>storeD);

AdderE: adder PORT MAP (new_term=>resultE, stored=>returnE,

result=>storeE);

AdderF: adder PORT MAP (new_term=>resultF, stored=>returnF,

result=>storeF);

Adder0: adder PORT MAP (new_term=>result0, stored=>return0,

result=>store0);

-------------------------------------------------------------------

PROCESS (clk,rst)

VARIABLE addr: INTEGER RANGE 0 TO 7;

BEGIN

addr := 0;

IF (addr < '7') THEN

IF (rst = '1') THEN

addr := 0;

ELSE IF (clk'EVENT AND clk = '1') THEN

west1 <= matrix_A(0)(addr);

west2 <= matrix_A(1)(addr);

west3 <= matrix_A(2)(addr);

west4 <= matrix_A(3)(addr);

north1 <= matrix_B(3)(addr);

north2 <= matrix_B(2)(addr);

north3 <= matrix_B(1)(addr);

north4 <= matrix_B(0)(addr);

addr := addr + 1;

END IF;

END IF;

END PROCESS;

END structure;