matrix array in vhdl

it depends. If you have an array of arrays, its going to be much easier:

type row_t is array(0 to 3) of std_logic_vector(7 downto 0);
  type matrix_t is array(0 to 3) of row_t;
  
  signal matrix   : matrix_t;
  signal temp_row : row_t;
  signal count    : unsigned(1 downto 0) := "00";
begin
  
  process(clk) 
  begin
    if rising_edge(clk) then
      temp_row <= matrix( to_integer(count) );
      
      count    <= count + 1;
    end if;
  end process;

If you're using a 2d, matrix type, things get a little more complicated as you have to use a function to extract the row, but it should generate the same logic.

type row_t is array(0 to 3) of std_logic_vector(7 downto 0);
  type matrix_t is array(0 to 3, 0 to 3) of std_logic_vector(7 downto 0);;
  
  signal matrix   : matrix_t;
  signal temp_row : row_t;
  signal count    : unsigned(1 downto 0) := "00";
  
  function extract_row( m : matrix_t; row : integer) return row_t is
    variable ret : row_t;
  begin
    for i in row_t'range loop
      ret(i)  := m(row, i);
    end loop;
    
    return ret;
  end function;
  
begin
  
  process(clk) 
  begin
    if rising_edge(clk) then
      temp_row <= extract_row( matrix, to_integer(count) );
      
      count    <= count + 1;
    end if;
  end process;

NB: Matrix could be an input to your entity.