Marvell 88EE1111 PHY tranciever MDIO reg configuration

Hello, I need some help.

I have an altera DE-115 which has two ethernet ports, all i want is to receive ethernet frame on ethernet port 1 and send that same frame from ethernet port 0. I can receive ethernet frame on fpga board from ethernet port 1 but cannot transmit that same frame from ethernet port 0. On both ports two different PC's are connected.

What changes should i make in this code

volatile int * tse = (int *) 0x00102000;

Initialize the MAC address

*(tse + 3) = 0x116E6001;

*(tse + 4) = 0x00000F02;

// Specify the addresses of the PHY devices to be accessed through MDIO interface

*(tse + 0x0F) = 0x10;

*(tse + 0x10) = 0x11;

Write to register 20 of the PHY chip for Ethernet port 0 to set up line loopback

*(tse + 0x94) = 0x4000;

// Write to register 16 of the PHY chip for Ethernet port 1 to enable automatic crossover for all modes("| = OR")

*(tse + 0xB0) = *(tse + 0xB0) | 0x0060;

// Write to register 20 of the PHY chip for Ethernet port 2 to set up delay for input/output clk

*(tse + 0xB4) = *(tse + 0xB4) | 0x0082;

// Software reset the second PHY chip and wait

*(tse + 0xA0) = *(tse + 0xA0) | 0x8000;

while ( *(tse + 0xA0) & 0x8000 )

;

// Enable read and write transfers, gigabit Ethernet operation, and CRC forwarding

*(tse + 2) = *(tse + 2) | 0x0000004B;