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Altera_Forum
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9 years ago

Marvell 88EE1111 PHY tranciever MDIO reg configuration

I'm trying to troubleshoot PHY for my dual Ethernet design on the DE2-115 Cyclone IV board. (I have to load my *.elf file twice for some reason for my design to work). In trying to figure ou...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
9 years ago

Hello!

Do you have your design working? I tried 88E1111 with Cyclone IV with GMII interface and the only result I have is correct RX (I see that in Signal Tap) and line loopback. All my attempts to transmit data is out of luck, internal loopback also keep silence. How to manage TX clocks? I suspect my problem in TX clocks - do you use PLL to generate TX clock with shifted phase?

Sorry for offtopic.