Honored Contributor
Honored ContributorA quick update to my problem. Thanks again bfkstimchan and kkaibara, I didn't get far with the GX approach, but I did have some success with my problem. I basically abandoned all hope of any IP solution and decided to make my own clock recovery circuit. I had an idea in mind which I found an almost exact match for with this guy's post.
http://www.twyman.org.uk/clock_recovery/ His approach seemed fairly sound for a slow recovery circuit so I implemented it and have found it to work. The one thing I will add for Altera users is I would advise using primitives for each element of the edges detector. As in, go instantiate DFF using the actual primitive instead of inferring through VHDL code. Same thing with the inverters - Actually instantiate an lpm_inv for each one. Then you have to generate a clock out of the sample[2] bit. The LPM_COUNTER, if you push down into it has flip flops at the outputs, so you can use the q of those to generate yyour recovered clock. As it was, here was my .sdf file entry to generate my recovered clock. create_generated_clock -name CDR_Recovered_clk -source [get_pins {slow_clock|altpll_component|auto_generated|pll1|clk[3]}] -divide_by 16 [get_pins {Inst_LS_XCVR_RX|\PLL_saver:CDR_DIG|sample_count|auto_generated|counter_reg_bit[3]|q}] Note: My oversampling clock for the digital CDR circuit was 16x the expected recovered clock. In the design reference that I posted above, he uses an 8x clock - I just wanted higher resolution. Therefore my recovered clock bit was [3] instead of [2]. And I had to tell it divide by 16 from my oversampling clock Therefore, Oversamplign clock was 320Mhz, and my recovered clock was 20Mhz. Works well!
