Forum Discussion
Altera_Forum
Honored Contributor
Honored ContributorMaking a counter from 50MHz Clock?
Hi, I know this might be a really silly question but I can't seem to get the theory down into HDL: I want to make a 3579545Hz clock from a 50MHz clock input: i know that --- Quote Start...
Altera_ForumHonored Contributor
Honored ContributorThe "others => '0' is equivalent to writing:
count := "000000000000000000000000000"; -- and I lost how many zeros. The subtraction is not to reset count to zero and you shouldn't. Instead you wrap up and keep difference from zero (count phase). To understand it better take case of generating 21MHz from 50MHz clock. the ratio factorises to 21/50 so: 0, + 21, + 21, + 21, + 21, + 21,... = 0, 21, 42, 63, 84, 105... and with modulo 50 = 0, 21, 42, 13, 34, 5... 0, 0, 1, 0, 1, 0... MSB will togle at 0.5 or more of count value
