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Altera_Forum's avatar
Altera_Forum
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13 years ago

Making a counter from 50MHz Clock?

Hi, I know this might be a really silly question but I can't seem to get the theory down into HDL: I want to make a 3579545Hz clock from a 50MHz clock input: i know that --- Quote Start...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

Wrong, I am afraid.

choose counter of 26 bits (to cover 50 million) and I will add extra bit for overflow protection. I prefer to use variable here so that the count is corrected before it is too late. 


process(clk)
variable count : unsigned(26 downto 0) := (others => '0');
begin
if rising_edge(clk) then
    if count > 50000000-1 then
         count := count - 50000000;
    else
         count := count + 3579545;
    end if;
    my_clk <= std_logic(count(25));
end if;
end process;