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Altera_Forum
Honored Contributor
Honored ContributorMaking a counter from 50MHz Clock?
Hi, I know this might be a really silly question but I can't seem to get the theory down into HDL: I want to make a 3579545Hz clock from a 50MHz clock input: i know that --- Quote Start...
Altera_ForumHonored Contributor
Honored ContributorYou have it in NCOs hidden there.
just use a suitable width adder starting from zero adding 3579545 every system clock and carrying over result after (50 million -1) i.e. if it becomes > (50 million-1) then subtract 50 million from it and keep going nonstop. Then MSB is your rate. The generated clock is correct rate-wise but duty cycle varies.
