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Altera_Forum's avatar
Altera_Forum
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16 years ago

Maintaining hierarchical names while doing timing simulation

Hi, I am running post place and route (timing) simulation in ModelSim. But all the wire and register names are modified and difficult to figure. How to maintain all the component names w...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

If you are using VHDL you can often label ifs, cases, processes, etc with a nice friendly descriptive name and then look for that name in the search and find your signals. Hope this helps a little.