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Altera_Forum's avatar
Altera_Forum
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17 years ago

Maintaining hierarchical names while doing timing simulation

Hi, I am running post place and route (timing) simulation in ModelSim. But all the wire and register names are modified and difficult to figure. How to maintain all the component names w...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

thank you for your responses.....

so does these signal have to be routed to the ports of the top most module?

cause i cannot see the port name of even intermediate level modules?