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Altera_Forum
Honored Contributor
Honored Contributorm9k memory blocks in cyclone3
hi i created ram with one read and one write port using megawizard function, while reading that memory 3 clock cycles delay is coming, can any one help me,
Altera_ForumHonored Contributor
Honored ContributorThere is a 1 clock cycle minimum delay to read data from the memory. Address is latched on 1st clock, data available on second.
Jake
