Altera_Forum
Honored Contributor
Honored Contributorm9k memory blocks in cyclone3
hi i created ram with one read and one write port using megawizard function, while reading that memory 3 clock cycles delay is coming, can any one help me,
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Altera_ForumHonored Contributor
Honored Contributorhi..thanks for ur reply...
i removed that output registering option... still i am getting one clock cycle delay while reading the data from that memory
