Altera_Forum
Honored Contributor
Honored Contributorm9k memory blocks in cyclone3
hi i created ram with one read and one write port using megawizard function, while reading that memory 3 clock cycles delay is coming, can any one help me,
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Altera_ForumHonored Contributor
Honored ContributorI think there is an option to register inputs and/or outputs so the clocks are needed for the registers. In effect there may be a 2 stage pipeline in the ram.
