Honored ContributorHi,
I was wondering why does the M9K block requires the read address bus to be registered but all the other pins can be driven from asynchronous logic? Regards
Honored ContributorI'm not aware of a family that uses the M9K blocks that can be controlled from asynchronous logic. All the input signals are registered: address, data, wren, rden (if used). You can choose not to register the output.
What device family and IP are you looking at? Looking at the 1-port & 2-port RAMs, there are grayed out options (perhaps) suggesting the data and other signals need not be registered. However, they're grayed out for a reason. Cheers, AlexHonored ContributorI am using a Cyclone IV with an implied RAM VHDL entity. I know that all the inputs a registered from the IP library, but you do not need to do that for the implied entity.
Honored ContributorYou can infer RAM in your code, that's fine. However, Quartus will only put it into a M9K block if it can find suitable registers in your code to match the structure of the M9K block. If there aren't registers in your code that Quartus can use as the input registers (i.e. without any other dependency on them) it won't use the block and will use registers to create the RAM.
So, if you use asynchronous control signals Quartus won't put your inferred RAM into an M9K block. That's just the way Altera have chosen to implement the M9K. Cheers, AlexHonored Contributor
