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The preferred way to implement LVDS signals (or other differential IO standards) is to use simple single ended ports in the top design (either HDL or schematic) and to assign LVDS I/O standard in the pin planner. The port has to be assigned to the positive LVDS pin, the negative pin is chosen automatically by the fitter.
All IP cores can be used in schematic design, symbols are generated on request.
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Thanks for your response.
Two more doubts
1. Shall i integrate counter IP and IBUF IP together as a single block design file, and import into QSYS. Please explain the process
2. Shall i call this IP in Qsys, and implement the bit file using NIOS because i need to verify the LVDS output.
Honored Contributor
