Honored ContributorLVDS Rx/Tx Issue
I need to interface a TI's time measuring unit (TMU) THS788 with an FPGA to get data from this TMU. The TMU has LVDS serial peripheral interface. It has Data (16 bit valid data, 1 start bit to indicate following valid data, and 2 end bits to indicate end of valid data), Clock (min speed 75MHz), and Strobe. All these signals are LVDS. Data is transmitted at the rising edge of Clock and when Strobe is logic 0. Its a classic SPI with LVDS standards. I wish to use a dedicated State Machine to read the data serially and put it in a register. I wish to possibly use the mega function ALTLVDS_Rx. I d not have a target FPGA, wish to use a small one (Max/cyclone). If this is possible, I request some directions to figure this out. I am back in this type of design after sometime. I am versed in Verilog, and have Quartus II 12.1. My development PC has no internet connection.
I will also need to develop similar interface for serial Tx module to command THS788. Thank you for your help.
