Forum Discussion
Honored ContributorLVDS power requirement
I am kind of confused with the contents of this link. Can anyone help?:confused::confused::confused: https://www.altera.com/support/support-resources/knowledge-base/solutions/rd04282010_33.html
7 Replies
Altera_ForumThere is more details explained from the other link:
https://www.altera.com/support/support-resources/knowledge-base/solutions/rd01242007_248.html Typically, we don't need to worry about how we power the LVDS buffer as LVDS is standard spec.- Altera_Forum
Hi Metaboy,
It is as the link mentioned, the differential voltage swing and the common mode should be your main concern instead of the voltage source. As long you Vpp of your IO meets the Vid of the device it should be fine. - Altera_Forum
You may refer to the device datasheet, look for "Differential I/O Standard Specifications" -> "LVDS" keywords to find out about the FPGA LVDS specs ie VOD, VCM and VID.
- Altera_Forum
means if I have a device with wide range of VCCIO, any reading within the spec will do?
- Altera_Forum
As long as the transmitter's output meet the receiver's output specs, it should be fine. You can also run signal integrity simulation to analyze if the signals are within specs.
- Altera_Forum
Yes, I agreed with tiny007's comments. Perhaps you can try out with Altera IBIS models simulation for quick verification
https://www.altera.com/support/support-resources/download/board-layout-test/ibis/ibs-ibis_index.html - Altera_Forum
Thanks everyone! I will try it out later! ;)
