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MK_ABQ's avatar
MK_ABQ
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3 months ago
Solved

LVDS pin detail on Arria 10

Hi, I am using Arria 10 FPGA in one of our project. OPN: 10AX066N2F40E1HG. I see that Bank 3D is dedicated to LVDS ( picture below from HW schematic). But, my FPGA pin planner says the pin ...
ShengN_altera's avatar
ShengN_altera
Icon for Super Contributor rankSuper Contributor
3 months ago

Hi,


Check this https://www.intel.com/content/www/us/en/docs/programmable/683461/current/i-o-and-differential-i-o-buffers-in-devices.html

LVDS I/O bank—supports differential and single-ended I/O standards up to 1.8 V. So you can use for single-ended.


If that IO you're using for LVDS SERDES, I don't think you can use 1.8V check this SERDES I/O Standards Support in Arria® 10 Devices https://www.intel.com/content/www/us/en/docs/programmable/683461/current/serdes-i-o-standards-support-in-devices.html


Thanks,

Regards,

Sheng