Forum Discussion
Honored ContributorLVDS I/O termination
Is an external 100Ohm resistor required at the input of an LVDS receiver I/O pair for the Cyclone III devices? The literature seems to suggest yes and no. Also, if I have "rx_in" as a single-channel LVDS serial input to my deserializer on the FPGA, is it correct to assume that "rx_in", and its complement "rx_in(n)" which the fitter autmoatically assigns, will be converted into a single serial bitstream by the LVDS I/O pair and presented to my deserializer as one rx_in?
12 Replies
Altera_Forum--- Quote Start --- It's not relevant since the differential inputs have dedicated terminations. The TCBs are for dynamic termination. --- Quote End --- Got it. Thank you very much for your help. :)- Altera_Forum
It's not relevant since the differential inputs have dedicated terminations. The TCBs are for dynamic termination.
- Altera_Forum
Initially, it was not on my either.
Right click on any column, Select "Customize columns" Add "Termination control Block" I'm assuming your project is already set to Stratix III. I'm not familiar with other parts so I don't know if the have this option. Thanks! - Altera_Forum
Funny, I can't see that column in my assignment editor or pin planner and I'm on 8.1. Where is it you see this column?
- Altera_Forum--- Quote Start --- Choose differential for LVDS inputs. --- Quote End --- Leave "Termination Control Block Column" blank? This column doesn't have pull down options. Thanks!
- Altera_Forum
Choose differential for LVDS inputs.
- Altera_Forum
Got it. It works.
One more question if I may: Regarding the 100 ohms differential termination on the LVDS input. What is the keyword to be selected on the "Input Termination" column? - OCT 100 ohms or - Differential or - Other (please specify) What about the "Termination Control" column? Thanks! - Altera_Forum
In Pin Planner (you have to add a respective column from the right-mouse context menu) or Assignment Editor.
- Altera_Forum
How do I set termination for LVDS Receiver in QuartusII 8.1. I'm using Stratix III FPGA.
Thanks! - Altera_Forum
I agree, that the requirement of external differential termination may be not that obvious.
However, there is a figure 8–2. typical lvds application, that shows the external termination. The verbose discussion of transmitter termination networks is necessary because of the different handling in row and column banks. If you are migrating from Cyclone or Cyclone II, you probably expect, that an external termination is necessary as with the predecessor, if you used Stratix before, you may expect an on-chip termination.
