LVDS interface between two boards with different fpga

Hi,
the preferred clocking scheme for fast serial interfaces is source synchronous with clock recovery from data stream ( CDR). Unfortunately Cyclone series doesn't offer generic CDR, except for Cyclone 10 GX. It's basically possible to implement soft CDR in FPGA fabric, but there are no Intel reference designs so far. Next best option is to send TX clock along with the data. Sending a frame clock with bit clock regeneration on the receiver side also solves the problem of frame synchronization.
You are apparently planning to distribute a master clock from the receiver, but it's still useful to return a TX clock for easier delay compensation (presumed you don't have a CDR option).