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Altera_Forum's avatar
Altera_Forum
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17 years ago

LVDS for between-board communication

I have saw the thread http://www.alteraforum.com/forum/showthread.php?t=3188&highlight=lvds (http://www.alteraforum.com/forum/showthread.php?t=3188&highlight=lvds).

In my project, i will use two boards to communicate, one is the transmitter,the other is the receiver. The data rate between them is over 200M. Can i use LVDS and 5UTP cable to connect the two boards? or any transmitter/receiver devices needed?

The FPGA on the two boards are EP2C5Q208C8N.

Thanks.

PS.FvM said "LVDS is good I/O standard for interchip and also interboard communication to my opinion" in the thread, does this sentence mean LVDS between-board communication is not the good choice?

3 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

    You may prefer external drivers, if you want to avoid any risk of external overvoltages damaging your FPGAs. Apart from this, a 200 MBps LVDS connection through CAT5 cables shouldn't be a problem.You should pay attention to keep the common mode voltage differences between the boards low.

  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

    Thanks very much,FVM.

    Maybe i need magnetic modules just like Ethernet network card to prevent external over-voltages.

    As CAT5 cables ,it is allowed to run high-speed protocols such as 100 Mbps Fast Ethernet and FDDI, can 200 MBps LVDS connection be OK? The data rate is related to the load resistance and the length of UTP.

    Maybe CAT6 cables is needed(it is for 1000 Mbps Fast Ethernet ) for longer distance transmission.
  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

    It's not that easy, I think. Ethernet transformers can be used only, if the LVDS data are 8B/10B coded or use another algorithm that generates a DC balanced bit stream. Another point is bit and frame synchronisation. A usual solution would be a source synchronous transmission, where you transmit a frame clock (lvds slow clock) through a second LVDS pair. The bit clock (lvds fast clock) is generated by a PLL at the receiver. With Cyclone II, no dynamical phase alignment is available, thus a sufficient low delay skew is required.

    An interesting solution is available in Stratix III with soft-cdr that allows to recover the clock from a single differential channel as usual with gigabit interfaces.