Honored Contributor
Honored ContributorIt's not that easy, I think. Ethernet transformers can be used only, if the LVDS data are 8B/10B coded or use another algorithm that generates a DC balanced bit stream. Another point is bit and frame synchronisation. A usual solution would be a source synchronous transmission, where you transmit a frame clock (lvds slow clock) through a second LVDS pair. The bit clock (lvds fast clock) is generated by a PLL at the receiver. With Cyclone II, no dynamical phase alignment is available, thus a sufficient low delay skew is required.
An interesting solution is available in Stratix III with soft-cdr that allows to recover the clock from a single differential channel as usual with gigabit interfaces.
