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Altera_Forum
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15 years ago

LVDS clock outputs

Hi all, We use Stratix-IV GX (EP4SG360FF35C4) device. 1. How to specify the PLL output clock as LVDS in altpll? (This device doesn't supports "Setup PLL in LVDS mode" option). 2. ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

Hi all,

I tried to implement this in a Cyclone II device, the way Jimbo recomended. For some reason the altDDIOs registers are not place in the IO cell, but logic cell out side it (see in the Chip Planner)

I have attached a simple example of what I'm fighting with

Cheers

Stefan