LVDS clock outputs

I suggest that rather than drive the clocks out directly from the PLL or through other I/Os, you use a 1-bit ALTDDIO_OUT MegaWizard for each of the clock outputs. When you do this, tie the HI data input to '1' and the LO data input to '0', and the same clock that is driving the data out to the select input. This will give you and edge-aligned clock. If you want center-aligned clock outputs, then shift the clock to the ALTDDIO_OUT by 90 degrees from the clock driving the data out. Using the ALTDDIO_OUT registers to drive your clock out will give you the lowest possible skew between your clock and your DDR data outputs.