LVDS characteristics of cyclonii DE1

hi all;

the circuit attached shows Sigma-Delta ADC that should be implemented on cycloneii DE1 EP2C20F484C7,and RC network; i want to design the RC network at the front end of circuit with the equations :

∆V[SUB]in[/SUB]/ V[SUB]CCIO[/SUB] = R1 / R2

∆V[SUB]in[/SUB] = (V[SUB]inMax[/SUB] – V[SUB]inMin[/SUB])

V[SUB]Ref[/SUB] = V[SUB]inMax[/SUB] × R2 / (R1 + R2)

Where :

∆V[SUB]in[/SUB] is the analog input voltage swing,

I have three questions:

1) what is the value of VCCIO? i found different values of 3.3 1.8 and don now use which one

2)and what is the permitted range for ∆V[SUB]in and Vref?

[/SUB]3)the output from LVDS is introduced as input, named (analog_cmp) for FPGA; now how should I apply pin assignment for (analog_cmp) in Quartusii?

thanks in advance.