LVDS Bitslip and Register Outputs

Hi folks,

I guess what I am after here is a little clarification. I have an LVDS receiver working (connected to an ADC), and when I generate a test pattern from the ADC I get the data but 'framed' incorrectly. There is a frame clock coming from the ADC but I have not connected it. On reading the LVDS megafucntion guide it looks like the bitslip port is just what I need, am I correct in thinking that I can simply pulse (adhering to the min/max requirements) until my data coming out matches what i expect to see? If so, what other considerations should I be aware of? ie 'add extra register for rx_data_align input port'??

Finally, can someone clarify what 'register outputs' means on the final config page of the megafunction? Is it a latched register with my data in such that I dont have to do it externally using the rx_outclock?

Many thanks for any advice

D