LVDS and single ended i/o

Question

Hi,

I need to connect a 16 bits lvds DAC to a FPGA. The FPGA is a EP3C40Q240C8N. It's possible, the FPGA have enought i/o lvds pins, but the i/o lvds pins are located on many banks. As result that it's impossible to connect an other component like a 16 bits adc (3.3V parallel bus datas) because only 1 tension level per bank is possible, many i/o pins are unavailable .

It's right ? Have I others solutions that use a FPGA with more pins ?

Thank

altera_forum · Answer

That's a good question, I'm wondering if you can feed the parallel 16bit adc with 2.5 V ? can you check the High and Low voltages limits for the adc ?

But the other constraints are that neighboring non-LVDS-PIO or PIOs on the same bank might disturb the LVDS lines.

http://www.altera.com/literature/an/an466.pdf

http://www.altera.com/literature/an/an479.pdf

Hope someone can give you a clearer answer...

altera_forum · Answer

The parallel 16 bits dac is the dac5681z by Texas Instruments :   The adc outputs levels are 0-2.5V or 0-3.3V.  If I can't mixed lvds and single i/o I must use an other FPGA.

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LVDS and single ended i/o

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