LVDS --- VCCIO voltage level (Stratix II GX)

Hello,

According to the Stratix II GX specification, to use a LVDS output port the VCCIO pin of the appropriate bank should provide 2.5 V. Unfortunately, the PCB with the FPGA has been already designed and mounted with VCCIO connected to 3.3 V. I don't have a schematic of Stratix's LVDS output buffers, so I would like to ask how the out of spec voltage may interfere the work of the buffers. I would expect a shifted cmmon-mode DC voltage. To cope with that issue, I have an idea to add capacitors which will AC-couple the LVDS output buffers of the Stratix II GX and input buffers of a destination device (to be more specific the LVDS input ports of the Virtex 5). Does anybody have any experience with such a configuration ? What kind of problems may emerge ? Thank you in advance.